Microelectronic integrated circuit device fabrication technology has focused on techniques and materials to produce smaller and faster devices for higher performance chips. This trend towards miniaturization has led to demand for improved semiconductor integrated circuit (IC) interconnect performance and improved manufacturability, resulting in a shift from conventional Al/SiO.sub.2 interconnect architectures to copper-based metallization in conjunction with low-permitivity dielectrics. Copper metallization reduces interconnect propagation delays, reduces cross-talk, and enables higher interconnect current densities with extended electromigration lifetime. When combined with low-k dielectrics, copper metallization can also decrease the number of metallization levels, resulting in reduced chip manufacturing costs. For instance, the superior electromigration performance and lower resistivity of copper compared to aluminum, permits a reduction in metal stack height that results in reduced signal cross-talk and improved interconnect speed.
A number of deposition methods, such as chemical-vapor deposition (CVD), physical-vapor deposition (PVD) and electrochemical deposition (ECD) or plating will support deposition of uniform thin-film copper layers. Chemical-vapor deposition, in particular, provides a number of advantages over other deposition techniques, including the capability for fully vacuum cluster integrated deposition of the diffusion barrier and copper layers through cluster tool equipment. Metal-organic CVD (MOCVD) is a particularly desirable means for deposition of copper due to its excellent gap-fill characteristics, such as is desirable for via holes and trenches, its excellent step coverage, its compatibility with single/dual damascene processing, and its relatively low thermal budget, such as less than 250.degree. C., which helps ensure compatibility with low-k polymer dielectrics. Due to these advantages, as device dimensions shrink, MOCVD is likely to replace other deposition techniques as the preferred solution for deposition of uniform high-conductivity copper layers.
Although copper provides a number of advantages for microelectronic chip performance, significant difficulties exist in depositing and reliably integrating copper layers on a substrate. One difficulty relates to copper's rapid diffusion through many materials, including both metals and dielectrics. Copper tends to diffuse through device materials during the thermal cycling that a semiconductor substrate experiences during the multi-level interconnect fabrication process, as well as during actual chip operation under applied electric fields. Copper diffusion into and/or through the inter-metal dielectric (IMD) results in current leakage between adjacent metal lines, known as line-to-line leakage. Copper diffusion through the IMD and pre-metal dielectric (PMD) or inter-level dielectric (ILD) and into the transistor regions results in degraded device characteristics and, potentially, non-functional transistor devices.
Another difficulty associated with copper in microelectronic device fabrication, such as semiconductor IC fabrication, is the sufficient adhesion of the copper to the underlying barrier. Moreover, copper is prone to corrosion and must be passivated. Non-conducting diffusion barriers, such as Si.sub.3 N.sub.4, are ideal for passivation and prevention of copper diffusion between metallization layers. However, for many applications, a conducting barrier is necessary. For instance, a conducting barrier is necessary to enable electrical current flow between via plugs and lower level metal lines. To reduce copper diffusion and corrosion, a number of advanced diffusion barriers have been developed to supplant traditional barriers used with aluminum and tungsten metallization, such as TiN and TiW barriers. For instance, some barriers proposed for use with copper metallization include Ta, TaN, WN.sub.x, and ternary barriers such as TiSiN, TaSiN, WSiN, and WBN. Although these barriers improve reliability of copper metallization in microelectronic devices, these conventional barriers have some significant difficultios including poor adhesion with as deposited copper and sometimes with other adjacent layers, such as low-K dielectrics.
Other potential problems associated with copper metallization include difficulties associated with the deposition process for depositing copper and barrier layers onto the substrate. The deposition of a barrier layer using conventional barrier materials and deposition techniques may have difficulty achieving a good nucleation surface to promote &lt;111&gt; texture in an overlying copper layer for improved electromigration lifetime, and good step coverage in high-aspect-ratio features so that barrier thickness on the sidewall and bottom is comparable to barrier thickness in the field. In addition, conventional barrier materials and deposition techniques tend to have increased resistivity, especially as deposition temperatures are lowered to below 380.degree. C.